Architecture design for new video coding and decoding standards seek tradeoffs that: lower die costs to a target budget, maintain die size to within a limited area, shorten time to market and permits some fixes to be applied as needed, while maximizing flexibility to allow implementation of as many existing and possible future codec standards as possible. Common solutions involve re-using previously existing hardwired blocks and then adding new blocks as each new standard develops. The conventional approaches involve guessing how undefined future codec standards might impact a current design.
Use of a reduced instruction set computer (RISC) central processor unit (CPU) in the design allows some of the standard processing to be implemented in software. The software, in turn, allows reusing the CPU hardware for many applications and for limited fixes to the hardware design. Some existing video codec designs implement a single-instruction stream multiple-data stream (SIMD) array processor to cover as many different standards as possible. Some filters and other hardwired blocks allow coefficients to be programmed, as parameters are determined after the hardware design has been completed. Hardware errors are commonly fixed by iterations of the die design and/or with software patches, where possible.
However, adding modules increases dies size and the amount of un-utilized hardware at any given moment. RISC CPUs are flexible, but lack in sheer speed for video tasks. Specialized SIMDs are good for an intended target. However, as with hardwired units, the flexibility added to a SIMD design to handle known standard variations causes inefficiencies in the hardware use. The inefficiencies increases die area and adaptation to new standards is not always good. Using programable coefficients for filters which only need fixed coefficients increases the filter size unnecessarily. Design changes at the die level to change the hardwired functions are costly and time consuming. Software patches can sometimes be applied, but usually result in some form of performance tradeoff which degrades operation.